Design and implementation of a QPSK demodulator using a central tendency technique
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Abstract
This paper describes a quadrature phase shift keying (QPSK) demodulator. The digital demodulator is based on the median for recovering data bits. The results showed that the median technique reduces complexity. The modulator consists of two different techniques: direct digital synthesis technique (DDS) and stored phases in read-only memories. These techniques were compared to probe the efficiency using parameters such as power consumption and the number of used elements. The modulator based on the memories is optimal. The modulator and demodulator were designed in VHDL language and were implemented in a Virtex-5 board from Xilinx.
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